1. Field of the Invention
The present invention relates to a semiconductor memory system equipped with a flash EEPROM (Electrically Erasable and Programable Read Only Memory) which is a non-volatile memory that is electrically and collectively erasable. More particularly, this invention relates to a semiconductor memory system that can employ an existing disk accessing scheme.
2. Description of the Related Art
Most conventional information processing system, such as a work station and a personal computer, use a magnetic disk drive as a memory device. The magnetic disk drive has advantages such as a high recording reliability and low bit price while having some short-comings such as its being large and susceptible to physical impact.
The operational principle of magnetic disk drives is to move a magnetic head on a rotating disk to write or read data on or from that disk. The mechanical moving portions, such as the rotatable disk and the magnetic head, may malfunction or may be damaged when a physical shock is applied to the disk drive. Further, the necessity of those mechanical movable portions gets in the way of making the whole drive compact.
To compensate for data when the aforementioned malfunction or damage occurs, conventionally, there is a technique of distributively storing data into a plurality of disk drives. This technique divides each word constituting data sent from a host system (computer main body) into predetermined bits and stores the data in the individual disk drives in that form. According to this technique, a spare disk drive for storing redundant or dummy data is provided to correct data even when one of a plurality of magnetic disk drives becomes entirely disabled.
As data is distributively stored into a plurality of disk drives to accomplish error correction according to this conventional technique, the length of one unit of data assigned to each disk drive is limited. According to this technique, after data is transferred to a magnetic disk drive, the transferred data is immediately recorded into a storage medium. To perform fast data reading/writing effectively using the performance of the magnetic disk drive, it is necessary to keep fast data transfer to the storage medium in a plurality of magnetic disk drives. Further, to read data from a plurality of disk drives, a buffer is necessary to restore a word that has been divided into predetermined bits.
Since magnetic disk drives require the mechanical movable portions as described above, it is difficult to make the entire disk drive compact. While such a magnetic disk drive will not raise any problem when used in a desktop computer which stays on a desk for usage, the aforementioned drawbacks become a bottleneck when it is used in a small portable laptop computer or notebook type computer.
Today, therefore, a lot of attention has been paid to a semiconductor disk drive which is small in size and is not susceptible to physical impact. Like the conventional magnetic disk drive, this semiconductor disk drive uses a flash EEPROM (Electrically Erasable and Programmable Read Only Memory), which is a non-volatile memory that is electrically and collectively erasable by the units of predetermined blocks, as a secondary memory device for a personal computer or the like. Like a DRAM (Dynamic Random Access Memory) and mask ROM (Read Only Memory) the flash EEPROM, which is also a semiconductor memory device, can achieve high density. As the semiconductor disk drive, unlike the magnetic disk drive, has no mechanical movable portions, it will not easily have a physical-impact oriented malfunction or damage. In addition, it has a smaller size which is advantageous.
Jpn. Pat. Appln. KOKAI Publication No. 4-57295, entitled "Electrically Programmable Memory Circuit," applied by NEC Corporation, discloses an example of a semiconductor disk drive which is designed to accomplish efficient data writing without wait using a plurality of semiconductor chips. The disclosed technique is designed to eliminate the wait time in one write cycle. This technology is targeted to an EEPROM as a semiconductor memory device. Normally, data is written byte by byte in an EEPROM in accordance with byte-by-byte data transfer. In a flash EEPROM, on the other hand, after data consisting of a predetermined number of consecutive bytes is transferred, it is written in the chips independently.
FIG. 1 illustrates an address which is sent to a semiconductor device (chip) from a host according to the technology by NEC Corporation. As shown in FIG. 1, predetermined bits of the address are used to control a CS (Chip Select) signal which selects one of a plurality of chips provided in the memory device. For instance, when four memory chips #0 to #3 are provided in the memory device as shown in FIG. 2, two bits in the logical address are used to control the CS signal. Those two bits are input to a predetermined decoder and is decoded into the CS signal there.
The upper and lower bits, excluding those two bits to control the CS signal, become a real memory address of that memory chip which become active by the CS signal. The number of the lower bits is enough to address the amount of data which can be written at a time, i.e., the amount of data which is written by the writing operation in one cycle. When 64-byte page writing is possible by the writing operation in one cycle for each of the memory chips #0 to #3, therefore, nine bits are assigned to the lower bits of the memory address so that 64 bytes can be addressed.
This bit assignment in the memory device provided with a plurality of memory chips can eliminate the wait time included in one writing cycle when data corresponding to consecutive addresses are written.
The continuous writing operation will now be described referring to FIGS. 2, 3A to 3E and 4A to 4D. Suppose that a semiconductor memory device is provided with the memory chips #0 to #3 as shown in FIG. 2, and those memory chips #0-#3 can each accomplish 64-byte page writing by one writing cycle. A write enable signal is output from the decoder to the memory chip #0 when predetermined two bits are "00," to the memory chip #1 when they are "01," the memory chip #2 when they are "10," and to the memory chip #3 when they are "11."
First, in writing data at consecutive address ("00000000000000000" to "000001001111111111") shown in FIGS. 3A-3E, as the predetermined bits in the data corresponding to the address shown in FIG. 3A are "00," the data is stored on one page (page A; see FIG. 2) corresponding to the address ("000000000000000" to "000000111111111") in the memory chip #0. Likewise, the data corresponding to the addresses shown in FIGS. 3B to 3D are stored in the areas which correspond to the address ("000000000000000" to "000000111111111") in the respective memory chips #1 to #3 (pages B-D; see FIG. 2). As the predetermined bits in the data corresponding to the address shown in FIG. 3E are "00," the data is stored on page E (see FIG. 2) corresponding to the addresses ("000001000000000" to "000001111111111") again in the memory chip #0.
The target memory chip for data writing therefore changes page by page in the order of #0, #1, #2, #3 and #0 again as shown in FIG. 2. Accordingly, the wait time becomes as shown in the timing charts given in FIGS. 4A to 4D; it is apparent that the wait time included in one writing cycle can be eliminated.
Since this scheme produces a CS signal by decoding predetermined bits in the address sent from a host, the addresses in each memory chip should be fixed in a consecutive order. If a specific area (block) becomes disabled due to deterioration or the like, therefore, data cannot be written at consecutive addresses including the address which corresponds to that area.
Suppose page B in the memory chip #1 shown in FIG. 2 is damaged and unaccessible. Then, since the addresses corresponding to the areas of pages A to E (the addresses sent from a host) are fixed and consecutive, page F cannot be used for the lost page B. It is apparent that while the scheme taught by NEC Corporation can eliminate the wait time included in one writing cycle, it cannot flexibly cope with a damage or the like of a memory area (block) which may be caused by deterioration or the like.
There is a so-called swapping process which is designed to cope with damaged blocks in a flash EEPROM which are originated from the frequent erasing/writing action or the like. This swapping process prevents the concentration of rewriting to a specific block in a flash EEPROM, whose rewrite count is limited, at the time data is written. In addition, the swapping processes is executed only in each flash EEPROM chip.
The swapping processes will be briefly described with reference to the flowchart illustrated in FIG. 5. The details of the swapping process are described in U.S. patent application Ser. No. 001,750.
To execute a swapping process, a memory area for storing data of the rewrite count is provided block by block in a flash EEPROM chip. This rewrite count data is incremented every time the accessed block is rewritten. In addition to the memory area for the rewrite count data, an area for storing the upper data (upper bits) of the rewrite count data of each block is provided. The upper data to be stored in this area is updated when a predetermined carry of the rewrite count (renewal of predetermined upper bits) occurs, and will not be updated every time a normal rewriting action is taken.
When a writing access to a designated address is requested under the above conditions, the block which corresponds to this designated address is accessed (steps A1 and A3). Then, the rewrite count data stored in the accessed block is incremented after which it is determined if a predetermined carry has occurred (steps A5 and A7).
When a predetermined carry occurs (YES in steps A7), it is determined if a swapping process should be performed, referring to the upper data of the rewrite count data (step A9). This decision on the swapping process is performed for example by comparing the upper data of the accessed block with the upper data of other blocks and detecting that block whose rewrite count is less by more than a predetermined number than the rewrite count of the accessed block. Consequently, the block whose rewire count is less by more than a predetermined number than the rewire count of the accessed block is selected and the execution of the swapping process is determined. Then, data to be written in the accessed block is replaced with the data that is held in the block selected in step A9 (step A11).
When data replacement is complete, a table which correlates the area for storing the upper data, the logical address and the real memory address with one another are changed (step A13).
When a predetermined carry has not occurred (No in step A7) or no block whose rewrite count is less by more than a predetermined number than the rewrite count of the accessed block has not been detected (NO in step A9), the swapping process will not be performed and the accessed block is entirely erased before the requested data is written there (step A15).
This swapping process prevents the concentration of rewriting to a specific block to thereby provide the average rewrite frequency for the individual blocks. It is therefore possible to prolong the service life of the individual blocks in a flash EEPROM whose rewrite counts are limited.
As mentioned above, the swapping of data is limited within each chip in this swapping process. While the rewriting frequencies of the individual block in each chip can be averaged, therefore, the average rewrite frequency cannot be provided for the individual chips provided in the semiconductor disk drive.
If a semiconductor disk drive using a flash EEPROM is used as a spare disk, the logical address sent from a host system is converted into the real address in the semiconductor disk drive. Normally, a plurality of semiconductor chips are populated on a semiconductor disk drive. The above address conversion is executed by correlating the track number and sector number given by the logical address from the host system to the real memory address by which the flash EEPROMs in the semiconductor disk drive are selectively accessed.
There is no established scheme for determining how to correlate the track number and sector number given by the logical address from the host system with the internal real memory address.
With a semiconductor disk drive in use, therefore, the conventional disk accessing scheme in the host system which arranges consecutive data within the same track to suppress the frequency per track as much as possible cannot be used effectively. In other words, conventionally, the conventional disk access scheme of the host system cannot be employed, making it difficult to effectively use a semiconductor disk drive as a spare disk.